The present invention relates to a pulsed static flip-flop for storing a logic state of a logic signal.
Flip-flops are used to rapidly store logic states, for example in pipeline stages of microprocessors. In this case, critical variables are the set-up time which indicates the temporal interval at which the logic level to be stored is changed with respect to a clock signal which defines the transparency of the flip-flop. Another important variable is the delay time tCLK-Q which denotes the temporal interval between a clock signal edge, which determines the transparency of the flip-flop, and the presence of the stored logic state at the output of the flip-flop. The hold time of a flip-flop is the minimum requisite time for which an input data item must remain at its signal level, after a clock edge which initiates the transparency, so that the data item is reliably stored in the flip-flop.
FIG. 1 illustrates a conventional clock-edge-controlled flip-flop MSFF comprising a master latch and a slave latch. The flip-flop MSFF comprises a data input DI, a clock input CLKI, and a data output QO. Provision is made of two latches LT1 and LT2 which each comprise a data input D11, D22, a data output Q11, Q22 and a clock input C1, C2. An input data item D is supplied to the data input D11 of the first latch LT1 and the output data item QI from the first latch LT1 is supplied to the data input D22 of the second latch LT2. The output data item Q can be tapped off from the output Q22 of the second latch LT2. A clock signal CLK is supplied to the clock input CLKI, said signal being inverted and delayed, via a first inverter I1, to form the delayed and inverted clock signal CLK′. The inverse clock signal CLK′ is supplied to the clock input C1 of the first latch LT1. The delayed clock signal CLK′ is also inverted by a second inverter 12 and, delayed further, is supplied, as a further clock signal CLK″, to the clock input C2 of the second latch LT2. Upon a rising clock edge of the clock signal CLK, the second latch LT2 is switched to be transparent and the first latch LT1 or the master latch is locked. As a result, the data item D is read into the master/slave flip-flop MSFF upon a rising clock edge and this state is output at the output QO over one clock period.
Such flip-flops are used, in particular, in pipeline stages of microprocessors. In this case, data are fed to the inputs of the flip-flops and further logic circuits are coupled to the output of a respective flip-flop. The respective logic operation of the logic circuit then provides a further input data item to a flip-flop which is coupled downstream. Chains of flip-flops and logic circuits are thus generally formed. Since the logic circuits have capacitances, they must be driven by the respective flip-flop. A requisite signal propagation time is also composed of the sum of tCLK-Q, tLOGIC and tSETUP, tCLK-Q being the delay time between a respective clock edge of the clock signal and an associated edge of the output data item, tLOGIC being the delay caused by the respective logic circuit, and tSETUP being the set-up time. The processing times and provision times are critical in microprocessors, in particular.